Varactor Q

These are notes from a cubicle discussion about choosing a varactor for a VCO.

At low RF frequencies, the varactor can be modeled as a capacitor in parallel with a resistor. Q=Rp/Xc = Rp*2*PI*f*C

Varactor Q varies with the reverse bias voltage applied to the PN junction. The larger the reverse bias, the larger the Q. Why does this occur? My coworker said at VR=0 or below 1V, the depletion region is narrower and thus there is more leakage current. This implies the resistance between the reverse biased PN junction is finite.



Choose a varactor so that VR>=1.5V to 2V at the maximum needed capacitance.

Maximize the difference in voltage between Cmin and Cmax. This reduces tuning sensitivity, which is good for phase noise, and keeps the varactor Q high.


My homework:
What is the behavior of the reverse leakage current vs. VR? I thought leakage current slowly increased until junction breakdown.

What does the equivalent Rp represent besides ohmic losses and leakage currents?

Does increasing VR decrease Cj?

How to deal with parasitic L's and C's?

Short Answer: Incorporate the parasitics into a filter structure.

You can't entirely eliminate the frequency rolloff due to parasitics, but you can reshape and push out the rolloff to a higher frequency. How is this possible? If there's a parasitic shunt C on the line, you can add series inductors or make the microstrip line inductive to form a "T" shaped low pass filter. Conversely, with a parasitic series L on the line, add shunt capacitors.

Common Mode Rejection Ratio CMRR

A real op-amp amplifies not only the differential voltage at its inputs, but also the common mode voltage. What is this common mode voltage? It's a voltage that is common to both inputs. For example if the input signals are riding on a fixed DC voltage, then that DC voltage is the common mode voltage. The common mode voltage can also be an AC voltage - the input signals are riding on a common carrier signal.

The gain applied to the differential signal and common mode signal is different. The ratio of the gains is the common mode rejection ratio. The larger the CMRR, the better the op-amp rejects the common mode signal.

CMRR = differential gain / common mode gain

The effect of CMRR can be modeled as an offset voltage = Vcm/CMRR , where Vcm is the common mode voltage.

Op-Amp Offset Voltage Vos

If the + and - inputs are shorted together, a real op-amp does not have 0V at the output. This occurs because each half of the input differential pair is not perfectly matched.

Vo=A*Vos , A is open loop gain

Vos can be modeled as a voltage source attached to the + terminal of an ideal op-amp.

Temperature effects:

Vos is affected by temperature and the temperature drift of Vos (dVos/dTemp) is on the spec-sheet.

Op-Amp Input Bias Current and Offset Current

I don't often design op-amp circuits and always need to remind myself of what are the non-ideal behaviors of real op-amps. Knowing about these characteristics is important especially if you are designing precision circuits for using in measurements and low signal levels.

1. Input Bias Current

Real op amps sink or source current through their input terminals. The input stage of all op amps is a differential pair made from either BJTs or FETs. The current arises from BJT's base current or the FET's gate leakage current. The FET's gate current is much less than the BJT's base current. The input current is also DIFFERENT between the + and - inputs due to slight mismatches between the transistors used in the differential pair.

IP = input bias current for + input
IN = input bias current for - input

On the spec sheet, the input bias current (IB) is the average of IP and IN. The difference between IP and IN is the input offset current (IOS).

How can IB and IOS cause problems?

If the resistances seen by the + and - terminals are different, then IB will generate a differential voltage across the input and this gets amplified. This can be alleviated by making the resistances identical. Even if the resistances are equal between the + and - terminals, IOS will still produce a differential voltage across the input. The only way to reduce its effects is to use lower values of resistors and use an op-amp with lower IOS.

Temperature effects:

IB decreases as temperature increases for a BJT input stage. Beta rises with temperature.

IB increases as T increases for FET input stage due to the reverse bias current doubling for every 10 degree C rise.

How to calculate S21, S11

S21 calculation

Connect a 2V, 50Ω source to the input of the two port network.
Connect 50Ω load to the output.
Calculate the voltage at the output.
This voltage is S21.

In dB, S21 magnitude = 20*log (Vout)

S11 calculation

Terminate output with 50Ω.
Calculate input impedance and reflection coefficient.

r = (Zin - 50Ω)/(Zin + 50Ω)

S11 (dB) = 20*log(r)


Single element two port networks

For a network with a single element (Z) in series between the input and output.
S21=2/(2+Z/Zo)
S11=Z/(2*Zo+Z)

For a network with a single shunt element (Y)
S21=2/(2+Y*Zo)
S11=-Y*Zo/(2+Y*Zo)