N-way Resistive Power Splitter

The "star" divider is a simple power splitter composed of equal value resistors connected to one common node. The isolation between outputs is the same as the insertion loss. Each input or output port is perfectly matched if the other ports are terminated with 50Ω.

R = 50Ω*(N-1)/(N+1), where N is the number of outputs.

Insertion Loss between ports = 20*log(1/N)


Example:
2 way splitter
N=2
R=50Ω*1/3=16.7Ω
Loss = 6 dB

Capacitor Selection for DC blocking

Richard Fiore of ATC wrote a good article about how to choose capacitors for DC blocking and bypassing applications. It originally appeared in the May 2001 issue of Applied Microwave and Wireless. The pdf (1.2 MB) is here and a similar web-friendly article is here.

The most surprising thing that I learned was that capacitors can be used in DC blocking or coupling applications even at frequencies above their series resonant frequency. The key point is making sure the magnitude of the impedance should be low to minimize insertion loss at the frequencies or band of operation.

A real capacitor can be modeled as with as series RLC circuit with Cp in parallel with the RL segment. The R represents the ESR and L is the parasitic inductance. As frequency increases, Xc decreases until reaching the series resonance frequency of L and C. At Fsr, the reactances cancel out and Xc only has a real component equal to the ESR. The plot of Xc vs. frequency shows a null, the depth of which depends on the ratio of the reactance at Fsr to ESR.

Above Fsr, Xc increases because the capacitor is now acting as an inductor. Eventually this parasitic inductance will resonant with the parasitic capacitance, Cp. At Fpar, Xc will peak. The peak impedance magnitude depends on the Q of the parallel tank circuit formed by L, Cp and R=ESR. Qpar=2*pi*Fpar*L/ESR. This peak will produce nulls in the insertion loss. Using the capacitor at Fpar may be acceptable depending on the depth of these nulls and application.


One final note is that the phase of the impedance will change abruptly at Fsr and Fpar. This is a consideration for phase sensitive applications in which the group delay must be constant within the signal bandwidth.

Transistor Selection for oscillators

Notes from a cubical discussion

Bias current should be kept low to reduce junction heating, which increases noise. On the other hand, reducing bias current does reduce FT. The transistor should have an FT 15-20 times greater than the oscillation frequency. It seems that the ideal transistor should have enough FT with low bias current, but this isn't the complete story. To get high FT at low bias current, the base width and area is made very small, but this raises the current density and junction heating, which increases noise. So the best transistor should have high enough FT at low bias currents without increasing noise too much.

The transistor in an oscillator circuit should never be saturated and never be cutoff. Overdriving the transistor increases phase noise. In a Colpitts configuration, where the feedback path is tapped off the emitter path and LC tank elements are on the base path, add anti-parallel pairs of diodes to the emitter path to ground. This will prevent the transistor going into cutoff mode.