RF Circuit Designer's Notes

Little nuggets of RF/analog circuit theory and design. Learn with me about PLLs, Q, noise, oscillators, filters, digital receiver concepts, etc.

Tuesday, November 25, 2008

sampling delay contribution to PLL phase margin

Sampling Delay becomes significant when the sampling frequency approaches the loop bandwidth.

Sampling delay (secs) = 1/Fpfd

The phase shift at open loop zero crossing frequency (~equal to closed loop bw, Fbw):

One period at Fbw = 1/Fbw = Tbw goes through a 360 degree phase shift.

sampling delay/Tbw = phase shift /360 degrees

phase shift = 360*td/Tbw = 360 * Fbw/Fpfd

The above relations hold true for ideal, impulse sampling.

In practice there is a hold circuit following the sampler, so that the delay is 0.5*Tsample. This results in a phase lag of 180*Fbw/Fpfd


At 9:31 AM, Blogger Custom Microwave said...

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