sampling delay contribution to PLL phase margin

Sampling Delay becomes significant when the sampling frequency approaches the loop bandwidth.

Sampling delay (secs) = 1/F_pfd

The phase shift at open loop zero crossing frequency (~equal to closed loop bw, Fbw):

One period at Fbw = 1/Fbw = Tbw goes through a 360 degree phase shift.

sampling delay/Tbw = phase shift /360 degrees

phase shift = 360*td/Tbw = 360 * Fbw/F_pfd

The above relations hold true for ideal, impulse sampling.

In practice there is a hold circuit following the sampler, so that the delay is 0.5*Tsample. This results in a phase lag of 180*Fbw/F_pfd

Input related spurs

Spurs on the LO at F_offset will manifest as a spur when the input signal frequency is offset by an equal amount.


F_offset = 200 khz on LO1
Fcenter =1G, F_LO1=5G (4GHz 1st IF)
Fspan = 10 MHz


Input signal = 999.8 MHz fed to spectrum analyzer
Display shows response at 999.8 MHz and 1000 MHz (due to lo spur)

If the RBW > 200kHz, would the power contributed by the LO spur affect the amplitude accuracy measurement of the main signal?
The detector determines power for a single point by looking at the power of IF spectrum limited by the RBW. Each display pixel is a bin consisting of several measurement points.

Determining Phase Shift from Zverev's Filter Book

Zverev's Filter book is the ultimate filter handbook, but it's not easy to use.

The attenuation and group delay plots are plotted vs. normalized frequency Ω, which is f/3dB cutoff frequency.

To figure out the phase shift, simply find the area under the group delay plot from 0 to the normalized frequency of interest.

Group Delay = - dφ/dΩ

Therefore

φ = ∫(TD*dΩ) from Ω=0 to Ω

Spectrum Analyzer Residual Spurious Response

When the RF input is terminated, the spectrum analyzer may still show discrete responses while the LO's are sweeping. This occurs because at certain LO frequencies, the harmonics of the first and second LO mix together forming a product that is equal to an IF frequency. If this "spurious" IF frequency gets into the IF path, the detector will see a signal and therefor the display will show a blip at the RF frequency where m*LO1-n*LO2 = +/-IF. IF can be any of the IF frequencies in the instrument.

Other possible residuals:

m*LO1-n*LO3
m*LO2-n*LO3
m*LOX-fixed frequency oscillation (due to cavity resonances, clock frequencies, etc..)

Anything leaking into the front end RF path before the first mixer

Measuring KP on PLL chip

this procedure measures the maximum charge pump current. The actual KP does not match exactly with the formula given for the current setting resistor.

CP outputs current pulses in which the duty cycle is proportional to frequency difference at the R and N divider output. When measuring current with the ammeter, the result is a average. This average current then varies according to the magnitude of the frequency error.
To measure the maximum current, ground either the RF or Ref input.

Disconnect CP output to ammeter. Connect other end of ammeter to Vp or ground depending on PFD polarity.

ADF411X PLL N counter, R counter range

Prescaler choices: 8/9, 16/17, 32/33, 64/65

RF/P <= 200 MHz


The N counter is acutally a dual modulus prescaler that is controlled by the A and B counters. Both A and B counters are toggled each time by the prescaler's output pulses. In operation, the RF signal is divided by P+1 A times and by P (B-A) times. Thus the net division is N=A*(P+1)+(B-A)*P

N= BP + A

A, B Ranges
B = 3 to 8191
A = 0 to 63

R counter range 1 to 16383

ADF411X PLL IC PD polarity

Phase Detector Polarity Bit
0 Negative
1 Positive

For PD=Positive
Ref/R > RF/N, CP sources current, Vt increases
Ref/R < RF/N, CP sinks current, Vt decreases.


For PD=Neg
RF/N > Ref/R, CP sources current, Vt increases
RF/N < Ref/R, CP sinks current, Vt decreases.




**In project, we use a 3200 mhz reference signal into the "RF" input and an IF signal into the "REF" input. The IF is obtained by mixing down or sampling the VCO frequency.** With a passive or non-inverting active loop filter, PD polarity should be Negative.

Links

Characteristic Impedance

http://www.belden.com/pdfs/Techpprs/ciocahalf.htm

http://sound.westhost.com/articles.htm

Controversial view on Electromagnetics Theory
http://www.ivorcatt.com/em_intro.htm

Varactor Q

These are notes from a cubicle discussion about choosing a varactor for a VCO.

At low RF frequencies, the varactor can be modeled as a capacitor in parallel with a resistor. Q=Rp/Xc = Rp*2*PI*f*C

Varactor Q varies with the reverse bias voltage applied to the PN junction. The larger the reverse bias, the larger the Q. Why does this occur? My coworker said at VR=0 or below 1V, the depletion region is narrower and thus there is more leakage current. This implies the resistance between the reverse biased PN junction is finite.



Choose a varactor so that VR>=1.5V to 2V at the maximum needed capacitance.

Maximize the difference in voltage between Cmin and Cmax. This reduces tuning sensitivity, which is good for phase noise, and keeps the varactor Q high.


My homework:
What is the behavior of the reverse leakage current vs. VR? I thought leakage current slowly increased until junction breakdown.

What does the equivalent Rp represent besides ohmic losses and leakage currents?

Does increasing VR decrease Cj?

How to deal with parasitic L's and C's?

Short Answer: Incorporate the parasitics into a filter structure.

You can't entirely eliminate the frequency rolloff due to parasitics, but you can reshape and push out the rolloff to a higher frequency. How is this possible? If there's a parasitic shunt C on the line, you can add series inductors or make the microstrip line inductive to form a "T" shaped low pass filter. Conversely, with a parasitic series L on the line, add shunt capacitors.