Digital Down Converters in Receivers

Why the heck do we need a DDC (digital downconverter) in receiver architectures with a DSP backend to do the IF processing?

Based on my textbook understanding of DSP, the analog IF signal should be sampled at 2*fmax, where fmax is the highest frequency signal, to avoid aliasing. Why do receivers need a DDC to reduce the sample rate and do some low pass filtering? Why can't the A/D sample rate be set to the reduced rate and have the DSP chip do all the filtering?

I finally read a clear explaination from R.N. Mutagi's article in RF Design, September 2004.

Analog signal should be oversampled for several reasons.

1. Quantization noise is spread out over wider spectral window (0-0.5*fsample). The total quantization noise power depends on the number of bits in the A/D. Its distribution is uniform across the spectral window. The wider the window (higher fs), the lower the noise level for the same amount of A/D bits.

2. In most receiver architectures, the A/D is preceded by an analog anti-alias filter (AKA prefilter). If we sample at fs=2*fmax, then that analog filter needs to have a steep cutoff at fs. A step cutoff filter is not easy to implement, especially if there are requirements for constant delay (linear phase). By oversampling, the filter's rolloff requirements are relaxed and easier to implement.

The downside of having a high fs is that the DSP may not be able to keep up to do REAL TIME processing. The DSP has to do all its operations on the present signal sample before the next sample arrives. That means all filtering, demodulation or whatever IF processing must be done in time < fs_new="N/M" fs="2fmax">>2*21.4 MHz or fs>>2*1MHz? It's the latter. I'll have a followup post to describe how to apply DSP to bandpass signals.