PLL Synthesizer Design

The main goal of PLL synthesizer designs is to optimize the VCO's phase noise with a lower phase noise reference, usually crystal-based. There is a tradeoff between tuning range and phase noise.


By overlaying the plots of the VCO phase noise and multiplied-up reference phase noise, one can see a frequency where the plots intersect. The composite phase noise plot is usually the multiplied-up reference phase noise near the carrier and the VCO itself far away from the carrier. With pictures it's easier to describe.

The intersection of the plots occurs at FC. This frequency will be the PLL's loop BW.

General method
1. Start with simple first order PLL loop (only one integrator-the VCO)
2. Determine loop gains needed to obtain FC.
T=KP*G*KV/(N*2pi*f)
KP units: V/radians (or A/radians for charge pump output)
KV units: Radians/(sec*V)
G: unitless or a transresistance for charge pump output
T=1 at f=FC

3. Now make loop 2nd order or higher. Add integrator (with pole at DC and zero)
Choose zero location based on acceptable phase margin at FC

4. Add other poles at f>FC due to VCO tuning bw, opamp pole, etc..
Calculated phase margin at FC

Quick estimate of phase lag or lead due to poles and zeros
Zeros
for fz < FC
+90-180/pi*(fz/FC)
for fz > FC
+180/pi*(FC/fz)

poles
for fp < FC
-90+180/pi*(fp/FC)

for fz > FC
-180/pi*(FC/fz)