RF Circuit Designer's Notes

sampling delay contribution to PLL phase margin

2008-11-25T09:12:00.000-08:00

Sampling Delay becomes significant when the sampling frequency approaches the loop bandwidth.Sampling delay (secs) = 1/FpfdThe phase shift at open loop zero crossing frequency (~equal to closed loop bw, Fbw):One period at Fbw = 1/Fbw = Tbw goes through a 360 degree phase shift.sampling delay/Tbw = phase shift /360 degreesphase shift = 360*td/Tbw = 360 * Fbw/FpfdThe above relations hold true for

Input related spurs

2008-11-25T08:56:00.000-08:00

Spurs on the LO at Foffset will manifest as a spur when the input signal frequency is offset by an equal amount.Foffset = 200 khz on LO1Fcenter =1G, FLO1=5G (4GHz 1st IF)Fspan = 10 MHzInput signal = 999.8 MHz fed to spectrum analyzerDisplay shows response at 999.8 MHz and 1000 MHz (due to lo spur)If the RBW > 200kHz, would the power contributed by the LO spur affect the amplitude accuracy

Determining Phase Shift from Zverev's Filter Book

2008-10-16T14:36:00.000-07:00

Zverev's Filter book is the ultimate filter handbook, but it's not easy to use.The attenuation and group delay plots are plotted vs. normalized frequency Ω, which is f/3dB cutoff frequency.To figure out the phase shift, simply find the area under the group delay plot from 0 to the normalized frequency of interest. Group Delay = - dφ/dΩThereforeφ = ∫(TD*dΩ) from Ω=0

Spectrum Analyzer Residual Spurious Response

2008-07-16T15:05:00.000-07:00

When the RF input is terminated, the spectrum analyzer may still show discrete responses while the LO's are sweeping. This occurs because at certain LO frequencies, the harmonics of the first and second LO mix together forming a product that is equal to an IF frequency. If this "spurious" IF frequency gets into the IF path, the detector will see a signal and therefor the display will show a blip

Measuring KP on PLL chip

2008-03-03T12:07:00.000-08:00

this procedure measures the maximum charge pump current. The actual KP does not match exactly with the formula given for the current setting resistor.CP outputs current pulses in which the duty cycle is proportional to frequency difference at the R and N divider output. When measuring current with the ammeter, the result is a average. This average current then varies according to the magnitude of

ADF411X PLL N counter, R counter range

2008-01-06T23:46:00.000-08:00

Prescaler choices: 8/9, 16/17, 32/33, 64/65RF/P <= 200 MHzThe N counter is acutally a dual modulus prescaler that is controlled by the A and B counters. Both A and B counters are toggled each time by the prescaler's output pulses. In operation, the RF signal is divided by P+1 A times and by P (B-A) times. Thus the net division is N=A*(P+1)+(B-A)*PN= BP + AA, B RangesB = 3 to 8191A = 0 to 63R

ADF411X PLL IC PD polarity

2008-01-06T23:39:00.000-08:00

Phase Detector Polarity Bit0 Negative1 PositiveFor PD=PositiveRef/R > RF/N, CP sources current, Vt increasesRef/R < RF/N, CP sinks current, Vt decreases.For PD=NegRF/N > Ref/R, CP sources current, Vt increases RF/N < Ref/R, CP sinks current, Vt decreases.**In project, we use a 3200 mhz reference signal into the "RF" input and an IF signal into the "REF" input. The IF is obtained by

Links

2007-01-26T17:58:00.000-08:00

Characteristic Impedancehttp://www.belden.com/pdfs/Techpprs/ciocahalf.htmhttp://sound.westhost.com/articles.htmControversial view on Electromagnetics Theoryhttp://www.ivorcatt.com/em_intro.htm

Varactor Q

2006-11-17T22:41:00.000-08:00

These are notes from a cubicle discussion about choosing a varactor for a VCO.At low RF frequencies, the varactor can be modeled as a capacitor in parallel with a resistor. Q=Rp/Xc = Rp*2*PI*f*CVaractor Q varies with the reverse bias voltage applied to the PN junction. The larger the reverse bias, the larger the Q. Why does this occur? My coworker said at VR=0 or below 1V, the depletion region is

How to deal with parasitic L's and C's?

2006-11-17T12:20:00.000-08:00

Short Answer: Incorporate the parasitics into a filter structure.You can't entirely eliminate the frequency rolloff due to parasitics, but you can reshape and push out the rolloff to a higher frequency. How is this possible? If there's a parasitic shunt C on the line, you can add series inductors or make the microstrip line inductive to form a "T" shaped low pass filter. Conversely, with a

Common Mode Rejection Ratio CMRR

2006-11-15T13:06:00.000-08:00

A real op-amp amplifies not only the differential voltage at its inputs, but also the common mode voltage. What is this common mode voltage? It's a voltage that is common to both inputs. For example if the input signals are riding on a fixed DC voltage, then that DC voltage is the common mode voltage. The common mode voltage can also be an AC voltage - the input signals are riding on a common

Op-Amp Offset Voltage Vos

2006-11-03T09:33:00.000-08:00

If the + and - inputs are shorted together, a real op-amp does not have 0V at the output. This occurs because each half of the input differential pair is not perfectly matched.Vo=A*Vos , A is open loop gainVos can be modeled as a voltage source attached to the + terminal of an ideal op-amp.Temperature effects:Vos is affected by temperature and the temperature drift of Vos (dVos/dTemp) is on the

Op-Amp Input Bias Current and Offset Current

2006-11-02T17:34:00.000-08:00

I don't often design op-amp circuits and always need to remind myself of what are the non-ideal behaviors of real op-amps. Knowing about these characteristics is important especially if you are designing precision circuits for using in measurements and low signal levels.1. Input Bias CurrentReal op amps sink or source current through their input terminals. The input stage of all op amps is a

How to calculate S21, S11

2006-11-01T10:53:00.000-08:00

S21 calculationConnect a 2V, 50Ω source to the input of the two port network.Connect 50Ω load to the output.Calculate the voltage at the output.This voltage is S21.In dB, S21 magnitude = 20*log (Vout)S11 calculationTerminate output with 50Ω.Calculate input impedance and reflection coefficient.r = (Zin - 50Ω)/(Zin + 50Ω)S11 (dB) = 20*log(r)Single element two port networksFor a network with a

N-way Resistive Power Splitter

2006-10-31T10:44:00.000-08:00

The "star" divider is a simple power splitter composed of equal value resistors connected to one common node. The isolation between outputs is the same as the insertion loss. Each input or output port is perfectly matched if the other ports are terminated with 50Ω.R = 50Ω*(N-1)/(N+1), where N is the number of outputs.Insertion Loss between ports = 20*log(1/N)Example:2 way splitterN=2R=50Ω*1/3=

Capacitor Selection for DC blocking

2006-10-27T13:55:00.000-07:00

Richard Fiore of ATC wrote a good article about how to choose capacitors for DC blocking and bypassing applications. It originally appeared in the May 2001 issue of Applied Microwave and Wireless. The pdf (1.2 MB) is here and a similar web-friendly article is here.The most surprising thing that I learned was that capacitors can be used in DC blocking or coupling applications even at frequencies

Transistor Selection for oscillators

2006-10-26T13:46:00.000-07:00

Notes from a cubical discussionBias current should be kept low to reduce junction heating, which increases noise. On the other hand, reducing bias current does reduce FT. The transistor should have an FT 15-20 times greater than the oscillation frequency. It seems that the ideal transistor should have enough FT with low bias current, but this isn't the complete story. To get high FT at low bias

PIN diode - self biasing limiter?

2005-03-02T18:03:00.000-08:00

I was having problems with using an antiparallel pair of PIN diodes as a limiter. The diodes were shunted between the RF line and ground. Since the turn on voltage is 0.76V, I expected the diodes to turn themselves on when the RF signal was > 8 dBm. They did not turn on.PIN diodes can not rectify high frequency f>>1/(2*pi*transit time) signals. Therefor the diode can not develop the DC bias to

YIG Oscillator - Ten Second Explaination

2004-11-17T18:08:00.000-08:00

David Straight wrote a good introduction on the basic physics behind the YIG oscillator.

Web blogs in technical communication

2004-11-16T19:30:00.000-08:00

Today I read an short article about the utility of blogs in technical communications. I've pasted the article here and the URL of the source. My comments are in blue text. Link Weblogs: Fad, or Future? -- document.write(get_publication('Test & Measurement World'));Test & Measurement World, 11/9/2004 10:55:00 AM Weblogs—or blogs, as the online, Web-based journals are called for

Digital Down Converters in Receivers

2004-11-11T13:25:00.000-08:00

Why the heck do we need a DDC (digital downconverter) in receiver architectures with a DSP backend to do the IF processing?Based on my textbook understanding of DSP, the analog IF signal should be sampled at 2*fmax, where fmax is the highest frequency signal, to avoid aliasing. Why do receivers need a DDC to reduce the sample rate and do some low pass filtering? Why can't the A/D sample rate be

Noise

2004-11-08T13:18:00.000-08:00

Noise has always been a confusing topic. The treatment of noise at the systems level and circuits level seems to be disjointed. The systems level treatment doesn't care about the particular details of the connections between each block. One assumption is that the blocks are all 50 ohms input and output. What happens to the noise when the blocks are not matched to each other? What if the port

Circular waveguides and the can-antenna for 802.11

2004-10-20T13:49:00.000-07:00

Circular waveguides used as antenna. TE11 mode D = 0.586*lambda_o TMo1 mode D = 0.766*lambda_o TE21 mode D=0.97*lambda_o Below cutoff, the signal is attenuated. Best to operate in TE11 mode. If other modes are excited, the antenna pattern will became skewed and the maximum will not be on the boresite. TM01 modes seem ok though. But for TE21 modes and higher, the pattern is skewed. The

PLL Synthesizer Design

2004-10-19T22:04:00.000-07:00

The main goal of PLL synthesizer designs is to optimize the VCO's phase noise with a lower phase noise reference, usually crystal-based. There is a tradeoff between tuning range and phase noise. By overlaying the plots of the VCO phase noise and multiplied-up reference phase noise, one can see a frequency where the plots intersect. The composite phase noise plot is usually the multiplied-up

book review

2004-10-14T03:49:00.000-07:00

I like amazon's book reviews of technical books. Most trade mags hype up the book and never say anything nasty. Circuit Design for Audio, AM/FM, and TV. Author: Texas Instruments pub in 1967!!!! I found this book in the library. I loved it. This presents lots of circuits with design procedures to make a real circuit with real circuit values. It's not a dumbed-down superficial cookbook. It has

Q -1

2004-10-12T21:55:00.000-07:00

Extra Element Theorem

2004-10-12T21:44:00.000-07:00

I was looking through my files and re-read an old article about the Extra Element Theorem. This theorem is cool because enables you to analyze a network by removing or adding an element that makes the analysis easier. For example, the input impedance of a bridge circuit with a load on the detection nodes. Without this theorem, I would have done the analysis using nodal or mesh analysis and coming

Broadband coupler

2004-10-09T18:34:00.000-07:00

I finally got the article that explains broadband coupler design. The coupler is based on the resistive bridge. The coupled port forms one of the arms of the bridge and it is also ground referenced. The DUT port forms another arm of the bridge. Unfortunately, that arm is not ground referenced. To measure a DUT that is ground referenced, a balun is needed to convert the DUT to floating load for

High Frequency Behavior of Ferrites

2004-10-07T21:43:00.000-07:00

I previously thought that the ferrite beads became lossy at high frequencies and that loss stays constant as f goes up. RB said a ferrite bead model is a parallel RLC circuit. At low frequencies, it is mostly inductive with resistive loss, then the inductive component decreases and the losses dominant. At sufficiently high frequency the parasitic capacitance between the ends of the bead begin to